Do you know how to solve the EMI problem when multi-layer PCB design?
Let me tell you!
There are many ways to solve EMI problems. Modern EMI suppression methods include: using EMI suppression coating, selecting appropriate EMI suppression parts and EMI simulation design. Based on the most basic PCB layout, this paper discusses the function of PCB stack in controlling EMI radiation and PCB design skills.
The output voltage jump of IC can be accelerated by placing appropriate capacitance near the power pin of IC. However, this is not the end of the problem. Due to the limited frequency response of the capacitor, it is impossible for the capacitor to generate the harmonic power needed to drive the IC output cleanly in the full frequency band. In addition, the transient voltage formed on the power bus will cause voltage drop at both ends of the inductance of the decoupling path. These transient voltages are the main common mode EMI interference sources. How can we solve these problems?
In the case of IC on our circuit board, the power layer around the IC can be regarded as a good high-frequency capacitor, which can collect the energy leaked by the discrete capacitor that provides high-frequency energy for clean output. In addition, the inductance of a good power layer is small, so the transient signal synthesized by the inductor is also small, thus reducing the common mode EMI.
Of course, the connection between the power supply layer and the IC power supply pin must be as short as possible, because the rising edge of the digital signal is faster and faster. It is better to connect it directly to the pad where the IC power pin is located, which needs to be discussed separately.
In order to control common mode EMI, the power layer must be a well-designed pair of power layers to help decouple and have a sufficiently low inductance. Some people may ask, how good is it? The answer depends on the power layer, the material between the layers, and the operating frequency (i.e., a function of IC rise time). In general, the spacing of power layers is 6mil, and the interlayer is FR4 material, so the equivalent capacitance per square inch of power layer is about 75pF. Obviously, the smaller the layer spacing, the larger the capacitance.
There are not many devices with a rise time of 100-300ps, but according to the current development rate of IC, the devices with rise time in the range of 100-300ps will occupy a high proportion. For circuits with 100 to 300 PS rise times, 3 mil layer spacing is no longer applicable for most applications. At that time, it is necessary to adopt the delamination technology with the interlayer spacing less than 1mil, and replace the FR4 dielectric material with the material with high dielectric constant. Now, ceramics and potted plastics can meet the design requirements of 100 to 300ps rise time circuits.
Although new materials and methods may be used in the future, common 1 to 3 ns rise time circuits, 3 to 6 mil layer spacing, and FR4 dielectric materials are usually sufficient to handle high-end harmonics and make transient signals low enough, that is, common mode EMI can be reduced very low. In this paper, the design example of PCB layered stacking is given, and the layer spacing is assumed to be 3 to 6 mil.
From the signal routing point of view, a good layering strategy should be to place all the signal traces in one or more layers, which are next to the power layer or ground plane. For power supply, a good layering strategy should be that the power layer is adjacent to the ground plane, and the distance between the power layer and the ground plane should be as small as possible, which is what we call the “layering” strategy.
What kind of stacking strategy can help shield and suppress EMI? The following layered stacking scheme assumes that the power supply current flows on a single layer and that single voltage or multiple voltages are distributed in different parts of the same layer. The case of multiple power layers will be discussed later.
There are some potential problems in the design of 4-ply laminates. First of all, even if the signal layer is in the outer layer and the power and ground plane are in the inner layer, the distance between the power layer and the ground plane is still too large.
If the cost requirement is the first, the following two alternatives to the traditional 4-ply board can be considered. Both of them can improve the EMI suppression performance, but they are only suitable for the case where the density of the components on the board is low enough and there is enough area around the components (to place the required copper coating for power supply).
The first is the preferred scheme. The outer layers of PCB are all layers, and the middle two layers are signal / power layers. The power supply on the signal layer is routed with wide lines, which makes the path impedance of power supply current low and the impedance of signal microstrip path low. From the perspective of EMI control, this is the best 4-layer PCB structure available. In the second scheme, the outer layer carries the power and ground, and the middle two layer carries the signal. Compared with the traditional 4-layer board, the improvement of this scheme is smaller, and the interlayer impedance is not as good as that of the traditional 4-layer board.
If the wiring impedance is to be controlled, the above stacking scheme should be very careful to lay the wiring under the copper island of power supply and grounding. In addition, the copper island on power supply or stratum should be interconnected as much as possible to ensure the connectivity between DC and low frequency.
If the density of the components on the 4-layer board is large, the 6-layer plate is better. However, the shielding effect of some stacking schemes in the design of 6-layer board is not good enough, and the transient signal of power bus is not reduced. Two examples are discussed below.
In the first case, the power supply and ground are placed in the second and fifth layers respectively. Due to the high impedance of copper clad power supply, it is very unfavorable to control the common mode EMI radiation. However, from the point of view of signal impedance control, this method is very correct.
In the second example, the power supply and ground are placed in the third and fourth layers respectively. This design solves the problem of copper clad impedance of power supply. Due to the poor electromagnetic shielding performance of layer 1 and layer 6, the differential mode EMI increases. If the number of signal lines on the two outer layers is the least and the length of the lines is very short (less than 1 / 20 of the highest harmonic wavelength of the signal), the design can solve the problem of differential mode EMI. The results show that the suppression of differential mode EMI is especially good when the outer layer is filled with copper and the copper clad area is grounded (every 1 / 20 wavelength interval). As mentioned above, copper shall be laid
Post time: Jul-29-2020